PDP-11π
ESP SoC design platform https://telegra.ph/ESP-01-12
ESP
The ESP Project page, platform for FPGA and ASIC SoC accelerator design, was significantly updated since the last time we mentioned it
Now it includes many more materials, guides and videos:
π‘ How to design accelerator in Vivado HLS and Mentor Graphics Catapult HLS
π¬ Describes HLS4ML Flow. Original HLS4ML papers covered only the core design path, but this guide help you to integrate the core into the computer system
πΊ Integrating with Nvidia GPUs sthrough NVDLA
π List of the related papers
ESP is run by the System-Level Design (SLD) group at Columbia University, led by Professor Luca P. Carloni.
The ESP Project page, platform for FPGA and ASIC SoC accelerator design, was significantly updated since the last time we mentioned it
Now it includes many more materials, guides and videos:
π‘ How to design accelerator in Vivado HLS and Mentor Graphics Catapult HLS
π¬ Describes HLS4ML Flow. Original HLS4ML papers covered only the core design path, but this guide help you to integrate the core into the computer system
πΊ Integrating with Nvidia GPUs sthrough NVDLA
π List of the related papers
ESP is run by the System-Level Design (SLD) group at Columbia University, led by Professor Luca P. Carloni.
ESP - open SoC platform
Documentation
The ESP website.
π€AMD Is in Advanced Talks to Buy Xilinx
by WSJ
πaccording to people familiar with the matter, in a deal that could be valued at more than $30 billion and mark the latest big tie-up in the rapidly consolidating semiconductor industry.
πAMDβs market value now tops $100 billion after its shares soared 89% this year as the coronavirus pandemic stokes demands for PCs, gaming consoles and other devices
πXilinx has a market value of about $26 billion, with its shares up about 9% so far this year, just ahead of the S&P 500βs 7% rise.
π¨βπ¨βπ¦Should AMD and Xilinx reach an agreement, three of the yearβs largest deals so far would be in the semiconductor industry
- Analog Devices paid 20B for Maxim Integrated
- Nvidia acquired ARM for 40B
by WSJ
πaccording to people familiar with the matter, in a deal that could be valued at more than $30 billion and mark the latest big tie-up in the rapidly consolidating semiconductor industry.
πAMDβs market value now tops $100 billion after its shares soared 89% this year as the coronavirus pandemic stokes demands for PCs, gaming consoles and other devices
πXilinx has a market value of about $26 billion, with its shares up about 9% so far this year, just ahead of the S&P 500βs 7% rise.
π¨βπ¨βπ¦Should AMD and Xilinx reach an agreement, three of the yearβs largest deals so far would be in the semiconductor industry
- Analog Devices paid 20B for Maxim Integrated
- Nvidia acquired ARM for 40B
WSJ
WSJ News Exclusive | AMD Is in Advanced Talks to Buy Xilinx
A deal between the rival chip makers could be worth more than $30 billion and mark the latest big tie-up in the rapidly consolidating industry.
π₯π―π€A boom in low cost edge AI chips using the RISC-V technology is coming says Facebookβs chief AI scientist Yann LeCun
πThe move to RISC-V for running neural networks for edge AI applications is accelerated by the proposed takeover of ARM by Nvidia, says Yann LeCun, chief AI scientist at Facebook speaking at the Innovation Day of French research lab CEA-Leti.
βThere is a change in the industry and ARM with Nvidia makes people uneasy but the emergence of RISC-V sees chips with a RISC-V core and an NPU (neural processing unit),β he said.
πβThese are incredibly cheap, less than $10, with many out of China, and these will become ubiquitous,β he said. βIβm wondering if RISC-V will take over the world there.β
πβCertainly edge AI is a super important topic,β he said. βIn the next two to three years, itβs not going to be exotic technologies, itβs about reducing the power consumption as much as possible, pruning the neural net, optimising the weights, shutting down parts of the system that arenβt used," said LeCun.
π€Ώ "The target is AR devices with chips in the next two to three years with devices in the five years, and thatβs coming,β he said.
πThe move to RISC-V for running neural networks for edge AI applications is accelerated by the proposed takeover of ARM by Nvidia, says Yann LeCun, chief AI scientist at Facebook speaking at the Innovation Day of French research lab CEA-Leti.
βThere is a change in the industry and ARM with Nvidia makes people uneasy but the emergence of RISC-V sees chips with a RISC-V core and an NPU (neural processing unit),β he said.
πβThese are incredibly cheap, less than $10, with many out of China, and these will become ubiquitous,β he said. βIβm wondering if RISC-V will take over the world there.β
πβCertainly edge AI is a super important topic,β he said. βIn the next two to three years, itβs not going to be exotic technologies, itβs about reducing the power consumption as much as possible, pruning the neural net, optimising the weights, shutting down parts of the system that arenβt used," said LeCun.
π€Ώ "The target is AR devices with chips in the next two to three years with devices in the five years, and thatβs coming,β he said.
eeNews Europe
RISC-V boom from edge AI says Facebook's chief AI scientist
A boom in low cost edge AI chips using the RISC-V technology is coming says Facebookβs chief AI scientist Yann LeCun
PDP-11π
β Can I run my Neural Network on the FPGA? β Does Vivado HLS run my CPP code on the FPGA? β What is difference between OneAPI and Intel OpenCL? β Vitis - is it a sort of HLS for VIvado, isn't it? π€ There are two main FPGA vendors today - Xilinx and Intel.β¦
2021_Book_DataParallelC.pdf
15.3 MB
Presentation by Philip Harris & Jeff Krupa (MIT)
Heterogeneous Computing at the LHC
π« Proton collisions (events) occurs at 40MHz in the CMS detector, a new collision each 25ns and there 8Mb of data per collision and it gives 320Tb/s. There's no chance to catch them all for now.
πΎ There are 3 triggering levels, that select only "interesting event" for offline-computing at rate 8Gb/s. ML Models (Decision Trees and DNNs) are used for events classification. It creates huge challenges both for throughput, and latency requirements.
βοΈ Described system integrates FPGAs and GPUs accelerators in the cloud through the network, to make it available for researches.
𧩠This huge and largescale work includes may famous institutions, among them Fermilab, MIT, CERN, AWS and Microsoft Brainwave project and can be applied not only to HEP, but also Astrophysics and Gravitational Wave Detection
- YouTube video
- Slides Link (Dropbox)
Heterogeneous Computing at the LHC
TL;DRπ FastML Collaboration is group founded by P.Harris and Nhan Tran to adapt DNN to LHC data flow, but already goes far beyond. HLS4ML tools is part of the project.
π« Proton collisions (events) occurs at 40MHz in the CMS detector, a new collision each 25ns and there 8Mb of data per collision and it gives 320Tb/s. There's no chance to catch them all for now.
πΎ There are 3 triggering levels, that select only "interesting event" for offline-computing at rate 8Gb/s. ML Models (Decision Trees and DNNs) are used for events classification. It creates huge challenges both for throughput, and latency requirements.
βοΈ Described system integrates FPGAs and GPUs accelerators in the cloud through the network, to make it available for researches.
𧩠This huge and largescale work includes may famous institutions, among them Fermilab, MIT, CERN, AWS and Microsoft Brainwave project and can be applied not only to HEP, but also Astrophysics and Gravitational Wave Detection
- YouTube video
- Slides Link (Dropbox)